1. Field of the Invention
The present invention relates to a delay locked loop. More specifically, the present invention relates to a voltage control delay loop (VCDL) forming a delay locked loop (DLL).
2. Description of the Prior Art
In the field of high-speed data communication, synchronization of data and a clock to be inputted has been an important technique.
For example, in a synchronization system in the field of high-speed data communication having a data transfer speed exceeding 2 gigabits/sec (Gbps), as one of means for uniformalizing the edges of a clock input and a data input, a DLL is used to cancel a propagation delay time in a buffer of a clock tree circuit (CT) in a chip (IC).
FIG. 4 is a block diagram of a delay locked loop (DLL) showing an example of such a prior art. As shown in FIG. 4, the DLL has a clock receiver 1 receiving a clock of 1.25 GHz inputted from a clock (CL) terminal; a delay circuit part 15 having n delay elements 16 connected in series for input and sequential delay of a reception clock (A) outputted from the clock receiver 1; a clock tree (CT) part 6 creating clocks (B) with the same timing based on an output of the delay circuit part 15; a phase control part 7 performing phase-control by the reception clock (A) and the clock (B) from the CT6 to on/off control the delay elements 16 of the delay circuit part 15; data receivers 8, 9 receiving data of 2.5 Gbps inputted from data input terminals (D0 to D15); and flip-flops (F/Fs) 10, 11 storing the data by reception outputs (C) of the data receivers 8, 9 and the clocks (B) from the DT part 6. The phase control part 7 is represented in one block, and has functions of phase detect, charge pump and low-pass filter. Only the two data receivers 8, 9 and only the two F/Fs 10, 11 are shown. The data receivers 8, 9 and the F/Fs 10, 11 are naturally provided corresponding to the number of the data input terminals.
Such DLL compensates for the clock delay variation of the CT part 6 by the phase control part 7 and the delay circuit part 15 and locks the clock (B).
FIG. 5 is a data and clock waveform chart of FIG. 4. As shown in FIG. 5, the rising edge of the clock (B) to be synchronized with the data (C) after one cycle of the reception clock (A) is a lock point (LP) via the delay circuit part 15 and the CT part 6 in the DLL. In other words, the clock (B) is locked at the rising edge of the clock (B). The clock (A) of 1.25 GHz is at a speed of 800 picoseconds (ps) in one clock cycle so as to mean that the total delay time of the delay circuit part 15 and the CT part 6 is 800 ps.
The data (C) is typically propagated in a timing delay 90 degrees in phase to the clock (A). When the data receivers 8, 9 are of the same construction (shape) and has the same performance, the timing shown in the drawing is maintained. For this reason, the flip-flops (F/Fs) 10, 11 can reliably receive the data (C) by the clocks (B) (that is, clocks 0 to 15) with the same timing.
FIG. 6 is a block diagram of the delay circuit part and the clock tree circuit shown in FIG. 4. As shown in FIG. 6, the basic circuit of the delay circuit part and the CT part 6 has differential NMOS transistors 20, 21 having gates to which clock input IN and IN inversion are supplied; load elements 17, 18 connected between the NMOSs 20, 21 and a power source VDD; and a constant current source 19 connected between the NMOSs 20, 21 and a ground GND. Clock output OUT and OUT inversion are taken out from the junctions of the NMOS transistors 21, 20 and the load elements 18, 17.
When the basic circuit is used in the delay elements 16 of the delay circuit part 15, the phase control part 7 variably controls the constant current source 19. The delay time of the delay circuit part 15 can be thus varied. As the load elements 17, 18 in the case of the delay circuit part 15, an active load of the NMOS transistor and a resistance load of high-resistance polysilicon are used. As the load elements 17, 18 in the case of the clock tree (CT) part 6, a resistance lead of high-resistance polysilicon is used.
The delay time of the above-mentioned prior art delay locked loop, particularly, the delay time of the clock tree (CT) part, largely depends on variation in the resistance elements forming the resistance loads.
When attempting to compensate for delay for the variation in the resistance elements only by a delay variation width generated by a current change of the current source of the delay circuit part, the resistance elements are return-controlled at the same time. A sufficient variation width cannot be compensated. As a result, a clock outputted from the CT part to the data processing part side cannot be locked. In other words, the lock point of the data and the clock cannot be determined.